/*++
THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
PARTICULAR PURPOSE.

Module Name:

pegdser_16950.h

Abstract:

Notes:

--*/

//	@doc	EXTERNAL SERIALDEVICE

#ifndef __PEGDSER_16950_H__

#define __PEGDSER_16950_H__

#ifdef __cplusplus
extern "C" {
    
#endif

// We'll need some defines

#include "..\..\..\public\common\oak\inc\windev.h"

//
// Vendor special DeviceIOControl dwIoControlCode values for 16950 ports
//
#define IOCTL_OX16950_GET_CRYSTALFREQUENCY     CTL_CODE(FILE_DEVICE_SERIAL_PORT,1001,METHOD_BUFFERED,FILE_ANY_ACCESS)
#define IOCTL_OX16950_SET_CRYSTALFREQUENCY     CTL_CODE(FILE_DEVICE_SERIAL_PORT,1002,METHOD_BUFFERED,FILE_ANY_ACCESS)
#define IOCTL_OX16950_GET_FIFO_LEVELS          CTL_CODE(FILE_DEVICE_SERIAL_PORT,1003,METHOD_BUFFERED,FILE_ANY_ACCESS)
#define IOCTL_OX16950_SET_FIFO_LEVELS          CTL_CODE(FILE_DEVICE_SERIAL_PORT,1004,METHOD_BUFFERED,FILE_ANY_ACCESS)
#define IOCTL_OX16950_GET_BAUDRATE_MAP         CTL_CODE(FILE_DEVICE_SERIAL_PORT,1005,METHOD_BUFFERED,FILE_ANY_ACCESS)
#define IOCTL_OX16950_SET_BAUDRATE_MAP         CTL_CODE(FILE_DEVICE_SERIAL_PORT,1006,METHOD_BUFFERED,FILE_ANY_ACCESS)
#define IOCTL_OX16950_SET_INTERNAL_LOOPBACK    CTL_CODE(FILE_DEVICE_SERIAL_PORT,1007,METHOD_BUFFERED,FILE_ANY_ACCESS)
#define IOCTL_OX16950_GET_LINE_DRIVER_CONTROLS CTL_CODE(FILE_DEVICE_SERIAL_PORT,1008,METHOD_BUFFERED,FILE_ANY_ACCESS)
#define IOCTL_OX16950_SET_LINE_DRIVER_CONTROLS CTL_CODE(FILE_DEVICE_SERIAL_PORT,1009,METHOD_BUFFERED,FILE_ANY_ACCESS)
#define IOCTL_OX16950_DETECT_XTAL_FREQ         CTL_CODE(FILE_DEVICE_SERIAL_PORT,1010,METHOD_BUFFERED,FILE_ANY_ACCESS)

// Structure used to specify fifo level controls

typedef struct
{
    UCHAR	ucTxIntTrigLevel;    // value of Transmit Fifo Interrupt Trigger Level
    UCHAR   ucTxIntTrigLevelMinimum;
    UCHAR   ucTxIntTrigLevelMaximum;
    UCHAR	ucRxIntTrigLevel;    // value of Receive Fifo Interrupt Trigger Level
    UCHAR   ucRxIntTrigLevelMinimum;
    UCHAR   ucRxIntTrigLevelMaximum;
    UCHAR	ucFlowCtrlLowLevel;  // value of Receive flow control on Level
    UCHAR   ucFlowCtrlLowLevelMinimum;
    UCHAR   ucFlowCtrlLowLevelMaximum;
    UCHAR	ucFlowCtrlHighLevel; // value of Receive flow control off Level
    UCHAR   ucFlowCtrlHighLevelMinimum;
    UCHAR   ucFlowCtrlHighLevelMaximum;
} FIFO_LEVEL_CTRL_VALS, *PFIFO_LEVEL_CTRL_VALS;

// Structure used to specify list of baudrate map pairs
#define BAUDRATE_MAP_LIST_LENGTH 16

typedef struct
{
    PDWORD pdwFrom;            // pointer to an array of baudbates to be mapped from
    PDWORD pdwTo;              // pointer to an Array of baudbates to be mapped to
    PDWORD pdwNumberOfPairs;   // pointer to number of baudrate pairs in the map list
} BAUDRATE_MAP, *PBAUDRATE_MAP;

enum
{
    LINE_DRIVER_CONTROL_NO_CONTROL  = 0,    // RS232c
    LINE_DRIVER_CONTROL_LOW_ENABLE  = 1,    // Low enable line drivers (most RS485/422)
    LINE_DRIVER_CONTROL_HIGH_ENABLE = 2,    // High enable line drivers
    LINE_DRIVER_CONTROL_INVALID
};

#define MAXIMUM_LINE_DRIVER_DELAY_BITS   15
#define MAXIMUM_LINE_DRIVER_DELAY_PHASES 15

typedef struct
{
    DWORD dwControl;
    BOOL  blDelaySupport;
    DWORD dwDelayBits;
    DWORD dwDelayPhases;
} LINE_DRIVER_CONTROL, *PLINE_DRIVER_CONTROL;

#define LINE_DRIVER_CONTROL_VAL_NAME      TEXT("LineDriverControl")
#define LINE_DRIVER_DELAY_BITS_VAL_NAME   TEXT("LineDriverDelayBits")
#define LINE_DRIVER_DELAY_PHASES_VAL_NAME TEXT("LineDriverDelayPhases")

#ifdef __cplusplus
}
#endif

#endif // __PEGDSER_16950_H__

